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FEATURES 14-Bit, 40/65 MSPS ADC Low Power: 550 mW at 65 MSPS 300 mW at 40 MSPS On-Chip Reference and Sample-and-Hold 750 MHz Analog Input Bandwidth SNR > 73 dBc to Nyquist @ 65 MSPS SFDR > 86 dBc to Nyquist @ 65 MSPS Differential Nonlinearity Error = 0.7 LSB Guaranteed No Missing Codes over Full Temperature Range 1 V to 2 V p-p Differential Full-Scale Analog Input Range Single 5 V Analog Supply, 3.3 V/5 V Driver Supply Out-of-Range Indicator Straight Binary or Twos Complement Output Data Clock Duty Cycle Stabilizer Output Enable Function 48-Lead LQFP Package APPLICATIONS Communications Subsystems (Microcell, Picocell) Medical and High End Imaging Equipment Ultrasound Equipment GENERAL DESCRIPTION
14-Bit, 40/65 MSPS A/D Converter AD9244
FUNCTIONAL BLOCK DIAGRAM
AVDD REFT REFB DRVDD
AD9244
VIN+ SHA VIN- TEN STAGE PIPELINE ADC DFS 14
CLK+ CLK- TIMING OUTPUT REGISTER OTR
DCS D13-D0 14 REFERENCE OEB
AGND CML VR
VREF SENSE
REF GND
DGND
PRODUCT HIGHLIGHTS
The AD9244 is a monolithic, single 5 V supply, 14-bit, 40 MSPS/65 MSPS analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier and voltage reference. The AD9244 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy at 40 MSPS/65 MSPS data rates and guarantees no missing codes over the full operating temperature range. The AD9244 has an on-board, programmable voltage reference. An external reference can also be used to suit the dc accuracy and temperature drift requirements of the application. A differential or single-ended clock input is used to control all internal conversion cycles. The digital output data can be presented in straight binary or in twos complement format. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9244 is available in a 48-lead low profile quad flatpack package (LQFP) and is specified for operation over the industrial temperature range (-40C to +85C).
Low Power--The AD9244, at 550 mW, consumes a fraction of the power of presently available ADCs in existing high speed solutions. IF Sampling--The AD9244 delivers outstanding performance at input frequencies beyond the first Nyquist zone. Sampling at 65 MSPS with an input frequency of 100 MHz, the AD9244 delivers 71 dB SNR and 86 dB SFDR. Pin Compatibility--The AD9244 offers a seamless migration from the 12-bit, 65 MSPS AD9226. On-Board Sample-and-Hold (SHA)--The versatile SHA input can be configured for either single-ended or differential inputs. Out-of-Range (OTR)--The OTR output bit indicates when the input signal is beyond the AD9244's input range. Single Supply--The AD9244 uses a single 5 V power supply, simplifying system power supply design. It also features a separate digital output driver supply to accommodate 3.3 V and 5 V logic families.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9244-SPECIFICATIONS
DC SPECIFICATIONS
Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error (EXT VREF)1 Gain Error (INT VREF)3 INTERNAL VOLTAGE REFERENCE Output Voltage Error (2 VREF) Load Regulation @ 1 mA Output Voltage Error (1 VREF) Load Regulation @ 0.5 mA Input Resistance INPUT REFERRED NOISE VREF = 2 V VREF = 1 V ANALOG INPUT Input Voltage Range (Differential) VREF = 2 V VREF = 1 V Common-Mode Voltage Input Capacitance4 Input Bias Current5 Analog Bandwidth (Full Power) POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD IDRVDD PSRR POWER CONSUMPTION DC Input6 Sine Wave Input
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (-65) or 40 MSPS (-40), Differential Clock Inputs, VREF = 2 V, External Reference, Differential Analog Inputs, unless otherwise noted.)
Test Level VI VI VI VI VI V V V V V VI V IV V V V V AD9244BST-65 Min Typ Max 14 Guaranteed 0.3 1.4 0.6 2.0 1.0 0.7 1.4 2.0 2.3 25 29 0.5 15 0.25 5 0.8 1.5 0.25 5 0.8 1.5 0.5 15 AD9244BST-40 Typ Max
Temp Full Full Full Full Full 25C Full Full Full Full Full Full Full Full Full 25C 25C
Min 14
Unit Bits
Guaranteed 0.3 0.6 0.6 1.3 2.0 2.3 25
1.4 2.0 1.0
Bits % FSR % FSR LSB LSB LSB ppm/C ppm/C ppm/C
29
mV mV mV mV k LSB rms LSB rms
Full Full Full 25C 25C 25C
V V V V V V
2 1 0.5 10 500 750 4 0.5
2 1 4 10 500 750
V p-p V p-p V pF A MHz
Full Full Full Full Full Full Full
IV IV V V V V VI
4.75 2.7
5
5.25 5.25
4.75 2.7
5
5.25 5.25
V V mA mA % FSR mW mW
109 12 0.05 550 590
64 8 0.05 300 345
640
370
NOTES 1 Gain error is based on the ADC only (with a fixed 2.0 V external reference). 2 Measured at maximum clock rate, f IN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Includes internal voltage reference error. 4 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2d for the equivalent analog input structure. 5 Input bias current is due to the inputs looking like a resistor that is dependent on the clock rate. 6 Measured with dc input at maximum clock rate. Specifications subject to change without notice.
-2-
REV. A
AD9244 AC SPECIFICATIONS
Parameter SNR fIN = 2.4 MHz fIN = 15.5 MHz (-1 dBFS) fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz SINAD fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz ENOB fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz THD fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz WORST 2 or 3 fIN = 2.4 MHz fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (-65) or 40 MSPS (-40), Differential Clock Inputs, VREF = 2 V, External Reference, AIN = -0.5 dBFS, Differential Analog Inputs, unless otherwise noted.)
Temp Full 25C Full 25C Full 25C Full 25C Full 25C 25C 25C Full 25C Full 25C Full 25C Full 25C 25C 25C Full 25C Full 25C Full 25C Full 25C 25C 25C Full 25C Full 25C Full 25C Full 25C 25C 25C 25C 25C 25C 25C 25C 25C Test Level VI I IV V VI I IV I IV V V V VI I VI I IV I IV V V V VI I VI I IV I IV V V V VI I VI I IV I IV V V V V V V V V V Min 72.4 74.8 72.0 73.7 72.1 74.7 70.8 73.0 69.9 72.2 71.2 67.2 72.2 74.7 72 74.4 70.6 72.6 69.7 71.9 71 59.8 11.7 12.1 11.7 12.1 11.4 11.8 11.3 11.7 11.5 9.6 -78.4 -90.0 -89.7 -80.4 -89.4 -79.2 -84.6 -78.7 -84.1 -83.0 -60.7 -94.5 -86.5 -86.1 -86.2 -60.7 -83.2 -56.6 -93.7 -92.8 11.7 9.1 -80.7 11.9 12.2 72.4 56.3 73.2 75.1 72.8 68.3 AD9244BST-65 Typ Max Min 73.4 75.3 AD9244BST-40 Typ Max Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
-84.5 -56.6
REV. A
-3-
AD9244 AC SPECIFICATIONS (continued)
Parameter SFDR fIN = 2.4 MHz fIN = 15.5 MHz (-1 dBFS) fIN = 20 MHz fIN = 32.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz Temp Full 25C Full 25C Full 25C Full 25C Full 25C 25C 25C Test Level VI I IV V IV I IV I IV V V V Min 78.6 94.5 83 90 81.4 91.8 80.0 86.4 79.5 86.1 86.2 60.7 84.5 56.6 AD9244BST-65 Typ Max Min 82.5 93.7 AD9244BST-40 Typ Max Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
DIGITAL SPECIFICATIONS
Parameter
(AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, External Reference, unless otherwise noted.)
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV V IV IV V IV IV V V IV IV IV IV IV IV IV IV AD9244BST-65 Min Typ Max 2 3.5 0.8 3.5 0.8 10 5 0.4 0.25 1.6 2 0.8 5 100 4.5 0.1 2.4 0.4 2.95 0.05 2.8 0.4 2.8 0.4 2.95 0.05 2.4 0.4 4.5 0.1 5 100 2 0.8 0.4 0.25 1.6 5 3.5 0.8 10 AD9244BST-40 Min Typ Max 2 3.5 0.8 Unit V V V V V A pF V p-p V V V V pF k V V V V V V V V
DIGITAL INPUTS Logic 1 Voltage (OEB, DRVDD = 3 V) Logic 1 Voltage (OEB, DRVDD = 5 V) Logic 0 Voltage (OEB) Logic 1 Voltage (DFS, DCS) Logic 0 Voltage (DFS, DCS) Input Current Input Capacitance CLOCK INPUT PARAMETERS Differential Input Voltage CLK-Voltage1 Internal Clock Common-Mode Single-Ended Input Voltage Logic 1 Voltage Logic 0 Voltage Input Capacitance Input Resistance DIGITAL OUTPUTS (DRVDD = 5 V)2 Logic 1 Voltage (IOH = 50 A) Logic 0 Voltage (IOL = 50 A) Logic 1 Voltage (IOH = 0.5 mA) Logic 0 Voltage (IOL = 1.6 mA) DIGITAL OUTPUTS (DRVDD = 3 V) Logic 1 Voltage (IOH = 50 A) Logic 0 Voltage (IOL = 50 A) Logic 1 Voltage (IOH = 0.5 mA) Logic 0 Voltage (IOL = 1.6 mA)
2
NOTES 1 See Clock section of Theory of Operation for more details. 2 Output voltage levels measured with 5 pF load on each output. Specifications subject to change without notice.
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REV. A
AD9244 SWITCHING SPECIFICATIONS
Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate Clock Period1 Clock Pulsewidth High2 Clock Pulsewidth Low2 Clock Pulsewidth High3 Clock Pulsewidth Low3 DATA OUTPUT PARAMETERS Output Delay (tPD)4 Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Enable Delay OUT-OF-RANGE RECOVERY TIME
(AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.)
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level VI V V V V V V V V V V V V AD9244BST-65 Min Typ Max 65 500 15.4 4 4 6.9 6.9 3.5 8 1.5 0.3 15 2 7 25 4 4 11.3 11.3 3.5 8 1.5 0.3 15 1 7 AD9244BST-40 Min Typ Max 40 500 Unit MHz kHz ns ns ns ns ns ns Clock Cycles ns ps rms ns Clock Cycles
NOTES 1 The clock period may be extended to 2 s with no degradation in specified performance at 25C. 2 With duty cycle stabilizer enabled. 3 With duty cycle stabilizer disabled. 4 Measured from clock 50% transition to data 50% transition with 5 pF load on each output. Specifications subject to change without notice
N+2 N+1 N ANALOG INPUT
N+3 N+4 N+5 N+6 N+7 N+8
N+9
tA
CLOCK
DATA N-9 OUT
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
tPD
Figure 1. Input Timing
REV. A
-5-
AD9244
ABSOLUTE MAXIMUM RATINGS 1
Mnemonic ELECTRICAL AVDD DRVDD AGND AVDD REFGND CLK+, CLK-, DCS DFS VIN+, VIN- VREF SENSE REFB, REFT CML VR OTR D0-D13 OEB
With Respect to Min Max AGND DGND DGND DRVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND DGND DGND DGND -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +6.5 +6.5 +0.3 +6.5 +0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 DRVDD + 0.3 DRVDD + 0.3
EXPLANATION OF TEST LEVELS Test Level
Unit V V V V V V V V V V V V V V V V C C C C
I. 100% production tested. II. 100% production tested at 25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
ENVIRONMENTAL2 Junction Temperature Storage Temperature Operating Temperature Lead Temperature (10 sec)
150 -65 +150 -40 +85 300
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical thermal impedances; JA = 50.0C/W; JC = 17.0C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
ORDERING GUIDE
Model AD9244BST-65 AD9244BST-40 AD9244BSTRL-65 AD9244BSTRL-40 AD9244-65PCB AD9244-40PCB
Temperature Range Package Description -40C to +85C -40C to +85C -40C to +85C -40C to +85C 48-Lead Low Profile Quad Flatpack Package 48-Lead Low Profile Quad Flatpack Package 48-Lead Low Profile Quad Flatpack Package 48-Lead Low Profile Quad Flatpack Package Evaluation Board Evaluation Board
Package Option ST-48 ST-48 ST-48 ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9244 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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REV. A
AD9244
PIN CONFIGURATION
REFGND REFB REFB VREF REFT REFT
VIN+
VIN-
CML
48 AGND AGND 1 2
47
46
45
44
43
DCS
NIC
VR
42
41
40
39
38
37 36 SENSE 35 DFS 34 AVDD 33 AGND 32 AGND
AVDD 3 AVDD 4 AGND 5 CLK- 6 CLK+ 7 NIC 8 OEB 9 D0 (LSB) 10 D1 11 D2 12 13
D3
AD9244
TOP VIEW (NOT TO SCALE)
31 AVDD 30 DGND 29 DRVDD 28 OTR 27 D13 (MSB) 26 D12 25 D11
14
DGND
15
DRVDD
16
D4
17
D5
18
D6
19
D7
20
D8
21
D9
22
DGND
23
DRVDD
24
D10
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 2, 5, 32, 33 3, 4, 31, 34 6, 7 8, 44 9 10 11-13, 16-21, 24-26 14, 22, 30 15, 23, 29 27 28 35 36 37 38 39-42 43 45 46, 47 48
Mnemonic AGND AVDD CLK-, CLK+ NIC OEB D0 (LSB) D1-D3, D4-D9, D10-D12 DGND DRVDD D13 (MSB) OTR DFS SENSE VREF REFGND REFB, REFT DCS CML VIN+, VIN- VR
Description Analog Ground. Analog Supply Voltage. Differential Clock Inputs. No Internal Connection. Digital Output Enable (Active Low). Least Significant Bit, Digital Output. Digital Outputs. Digital Ground. Digital Supply Voltage. Most Significant Bit, Digital Output. Out-of-Range Indicator (Logic 1 indicates OTR). Data Format Select. Connect to AGND for straight binary, AVDD for twos complement. Internal Reference Control. Internal Reference. Reference Ground. Internal Reference Decoupling. 50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND for external control of both clock edges. Common-Mode Reference (0.5 x AVDD). Differential Analog Inputs. Internal Bias Decoupling.
REV. A
-7-
AD9244
TERMINOLOGY Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
sampled signal does not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (noise caused by jitter increases as the input frequency increases).
Integral Nonlinearity (INL)
The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Voltage Range
INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
Minimum Conversion Rate
The peak-to-peak differential voltage must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the input phase 180 and taking the peak measurement again. Then the difference is found between the two peak measurements.
Differential Nonlinearity (DNL, No Missing Codes)
The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Nyquist Sampling
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges.
Dual Tone SFDR*
When the frequency components of the analog input are below the Nyquist frequency (fCLOCK/2), this is often referred to as Nyquist sampling.
Out-of-Range Recovery Time
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.
Effective Number of Bits (ENOB)
The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at its minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise-and-Distortion (SINAD)*
The effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula: N = (SINAD - 1.76) / 6.02
Gain Error
The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)*
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last code transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
Common-Mode Rejection Ratio (CMRR)
The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)*
The difference in dB between the rms amplitude of the input signal and the peak spurious signal.
Temperature Drift
Common-mode (CM) signals appearing on VIN+ and VIN- are ideally rejected by the differential front end of the ADC. With a full-scale CM signal driving both VIN+ and VIN-, CMRR is the ratio of the amplitude of the full-scale input CM signal to the amplitude of signal that is not rejected, expressed in dBFS.
IF Sampling
The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX.
Total Harmonic Distortion (THD)*
The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal.
Offset Error
Due to the effects of aliasing, an ADC is not necessarily limited to Nyquist sampling. Higher sampled frequencies will be aliased down into the first Nyquist zone (DC-fCLOCK/2) on the output of the ADC. Care must be taken that the bandwidth of the
The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point.
*AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
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REV. A
AD9244
DRVDD DRVDD AVDD
DRVDD
CLK BUFFER
200
200
DGND
DGND
AGND
a. D0-D13, OTR
b. Three-State (OEB)
c. CLK+, CLK-
AVDD
AVDD
AVDD
200
AGND
AGND
AGND
d. VIN+, VIN-
e. DFS, DCS, SENSE Figure 2. Equivalent Circuits
f. VREF, REFT, REFB, VR, CML
REV. A
-9-
AD9244-Typical Performance Characteristics
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Duty Cycle Stabilizer Enabled, TA = 25 C, Differential Analog Input, Common-Mode Voltage (VCM) = 2.5 V, Input Amplitude (AIN) = -0.5 dBFS, VREF = 2.0 V External, FFT length = 8 K, unless otherwise noted.)
0 SNR = 74.8dBc SFDR = 93.6dBc -20
90 SFDR - dBFS SFDR - dBc
dBFS AND dBc
100
AMPLITUDE - dBFS
-40
80 SNR - dBFS 70 SFDR = 90dBc REFERENCE LINE
-60
-80
60
SNR - dBc
-100
50
-120 0 5 10 15 20 FREQUENCY - MHz 25 30 32.5
40 -30 -25 -20 -15 AIN - dBFS -10 -5 0
TPC 1. Single-Tone FFT, fIN = 5 MHz
TPC 4. Single-Tone SNR/SFDR vs. AIN, fIN = 5 MHz
0 SNR = 74.0dBc SFDR = 87.0dBc -20
100 SFDR - dBFS 90
AMPLITUDE - dBFS
-60
dBFS AND dBc
-40
80
SNR - dBFS SFDR - dBc SFDR = 90dBc REFERENCE LINE
70
-80
60
-100
50 SNR - dBc
-120 0 5 10 15 20 FREQUENCY - MHz 25 30 32.5
40 -30
-25
-20
-15 AIN - dBFS
-10
-5
0
TPC 2. Single-Tone FFT, fIN = 31 MHz
TPC 5. Single-Tone SNR/SFDR vs AIN, fIN = 31 MHz
0 SNR = 68.0dBc SFDR = 59.5dBc -20
100
90 SFDR - dBFS
AMPLITUDE - dBFS
-40
dBFS AND dBc
80
SNR - dBFS SFDR - dBc
-60
70
-80
60
SFDR = 90dBc REFERENCE LINE SNR - dBc
-100
50
-120 0 5 10 15 20 FREQUENCY - MHz 25 30 30.72
40 -30
-25
-20
-15 AIN - dBFS
-10
-5
0
TPC 3. Single-Tone FFT, fIN = 190 MHz, fSAMPLE = 61.44 MSPS
TPC 6. Single-Tone SNR/SFDR vs. AIN, fIN = 190 MHz, fSAMPLE = 61.44 MSPS
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REV. A
AD9244
75 12.2
75
73
11.8
73
SINAD - dBc
2V SPAN 69 11.2
SNR - dBc
71
11.5
ENOB - Bits
71
2V SPAN
69 1V SPAN
1V SPAN 67 10.8
67
65 0 20 40 60 80 100 120 INPUT FREQUENCY - MHz
10.5 140
65
0
20
40 60 80 100 INPUT FREQUENCY - MHz
120
140
TPC 7. SINAD/ENOB vs. Input Frequency
TPC 10. SNR vs. Input Frequency
-100
100
-95
95 1V SPAN
1V SPAN -85
SFDR - dBc
THD - dBc
-90
90
85
-80
2V SPAN
80
2V SPAN
-75
0
20
40 60 80 100 INPUT FREQUENCY - MHz
120
140
75 0 20 40 60 80 100 INPUT FREQUENCY - MHz 120 140
TPC 8. THD vs. Input Frequency
TPC 11. SFDR vs. Input Frequency
77
-92 -90
75 +25 C
-88 -86 +25 C -40 C
SNR - dBc
THD - dBc
73 -40 C 71
-84 -82 -80 +85 C -78
69 +85 C 67 -76 -74 0 20 40 60 80 100 INPUT FREQUENCY - MHz 120 140 0 20 40 60 80 100 INPUT FREQUENCY - MHz 120 140
TPC 9. SNR vs. Temperature and Input Frequency
TPC 12. THD vs. Temperature and Input Frequency
REV. A
-11-
AD9244
-100
100 95
-95
FOURTH HARMONIC THIRD HARMONIC
90
SNR/SFDR - dBc
SFDR, DCS ON
HARMONICS - dBc
-90
85 80 75 SNR, DCS ON 70 SFDR, DCS OFF
-85
-80
SECOND HARMONIC
65 SNR, DCS OFF 60
-75
0
20
40
60
80
100
120
140
30
35
40
INPUT FREQUENCY - MHz
45 50 55 DUTY CYCLE - %
60
65
70
TPC 13. Harmonics vs. Input Frequency
TPC 16. SNR/SFDR vs. Duty Cycle, fIN = 2.5 MHz
76 fIN = 2MHz 75
12.33
100 fIN = 2MHz
12.17
96
74
SINAD - dBc
12.00
ENOB - Bits
SFDR - dBc
fIN = 10MHz 73 fIN = 20MHz 72 11.67 11.83
92 fIN = 10MHz 88
71
11.50
84
fIN = 20MHz
70 0 20 40 60 SAMPLE RATE - MSPS 80
11.34 100
80
0
20
40
60
80
100
SAMPLE RATE - MSPS
TPC 14. SINAD vs. Sample Rate
TPC 17. SFDR vs. Sample Rate
1.5
1.0 0.8
1.0
0.6
0.5
INL - LSB
0.4
0
DNL - LSB
0.2 0 -0.2 -0.4
-0.5
-1.0
-0.6 -0.8
-1.5 0 4096 8192 CODES - 14-Bit 12288 16384
-1.0
0
4096
8192 CODES - 14-Bit
12288
16384
TPC 15. Typical INL
TPC 18. Typical DNL
-12-
REV. A
AD9244
TYPICAL IF SAMPLING PERFORMANCE
0 SNR = 67.5dBc SFDR = 79.4dBc -20
100 SFDR - dBFS 90 SFDR - dBc
AMPLITUDE - dBFS
dBFS AND dBc
-40
80 SNR - dBFS 70 SFDR = 90dBc REFERENCE LINE SNR - dBc
-60
-80
60
-100
50
-120
0
5
10
15 20 FREQUENCY - MHz
25
30 32.5
40 -30
-25
-20 -15 AIN - dBFS
-10
-6
TPC 19. Dual-Tone FFT with fIN-1 = 44.2 MHz and fIN-2 = 45.6 MHz (AIN1 = AIN2 = -6.5 dBFS)
TPC 22. Dual-Tone SNR/SFDR vs. AIN with fIN-1 = 44.2 MHz and fIN-2 = 45.6 MHz
0 SNR = 67.0dBc SFDR = 78.2dBc -20
100
90
SFDR - dBFS
AMPLITUDE - dBFS
-40 dBFS AND dBc
80
SNR - dBFS
-60
70
SFDR - dBc SFDR = 90dBc REFERENCE LINE
-80
60
-100
50 SNR - dBc
-120
0
5
10
15 20 FREQUENCY - MHz
25
30 32.5
40 -30
-25
-20 -15 AIN - dBFS
-10
-6
TPC 20. Dual-Tone FFT with fIN-1 = 69.2 MHz and fIN-2 = 70.6 MHz (AIN1 = AIN2 = -6.5 dBFS)
0 SNR = 65.0dBc SFDR = 69.1dBc -20
TPC 23. Dual-Tone SNR/SFDR vs. AIN with fIN-1 = 69.2 MHz and fIN-2 = 70.6 MHz
100 SFDR - dBFS 90
AMPLITUDE - dBFS
-40
dBFS AND dBc
80 SNR - dBFS 70 SFDR - dBc 60 SFDR = 90dBc REFERENCE LINE
-60
-80
-100
50 SNR - dBc
-120 0 5 10 15 20 FREQUENCY - MHz 25 30 32.5
40 -30 -25 -20 -15 AIN - dBFS -10 -6
TPC 21. Dual-Tone FFT with fIN-1 = 139.2 MHz and fIN-2 = 140.7 MHz (AIN1 = AIN2 = -6.5 dBFS)
TPC 24. Dual-Tone SNR/SFDR vs. AIN with fIN-1 = 139.2 MHz and fIN-2 = 140.7 MHz
REV. A
-13-
AD9244
0 SNR = 62.6dBc SFDR = 60.7dBc -20
90 SFDR - dBFS 100
AMPLITUDE - dBFS
-40
dBFS AND dBc
80
SNR - dBFS
-60
70 SFDR - dBc 60 SFDR = 90dBc REFERENCE LINE
-80
-100
50 SNR - dBc
-120
0
5
10
15 20 FREQUENCY - MHz
25
30 32.5
40 -30
-25
-20 -15 AIN - dBFS
-10
-6
TPC 25. Dual-Tone FFT with fIN-1 = 239.1 MHz and fIN-2 = 240.7 MHz (AIN-1 = AIN2 = -6.5 dBFS)
TPC 28. Dual-Tone SNR/SFDR vs. AIN with fIN-1 = 239.1 MHz and fIN-2 = 240.7 MHz
0 SNR = 73.0dBFS THD = -89.5dBFS -20
95 SFDR - dBFS 90 SFDR - dBc 85
AMPLITUDE - dBFS
-40 NOTE: SPUR FLOOR BELOW 90dBFS @ 240MHz -60
dBFS AND dBc
80 SNR - dBFS 75 70 65 SFDR = 90dBc REFERENCE LINE
-80
-100
60
SNR - dBc
-120
0
5
10
15 20 FREQUENCY - MHz
25
30 32.5
55 -21
-18
-15
-12 -9 AIN - dBFS
-6
-3
0
TPC 26. Driving ADC Inputs with Transformer and Balun, fIN = 240 MHz, AIN = -8.5 dBFS
TPC 29. Driving ADC Inputs with Transformer and Balun SNR/SFDR vs. AIN, fIN = 240 MHz
105 100 95
95 SFDR - dBFS 90 85 SFDR - dBc
dBFS AND dBc
AMPLITUDE - dBFS
90 85 80 75 70 65
80 75 70 65 SNR - dBc 60 55 -21 SFDR = 90dBc REFERENCE LINE SNR - dBFS
0
50
100 150 INPUT FREQUENCY - MHz
200
250
-18
-15
-12 -9 AIN - dBFS
-6
-3
0
TPC 27. CMRR vs. Input Frequency (AIN = 0 dBFS and CML = 2.5 V)
TPC 30. Driving ADC Inputs with Transformer and Balun SNR/SFDR vs. AIN, fIN = 190 MHz
-14-
REV. A
AD9244
THEORY OF OPERATION
2.5V 1.5V 50 33 2V 2.5V 1.5V + 10 F 0.1 F SENSE REFGND 33 20pF VIN- VREF REFT 0.1 F REFB 0.1 F 10 F +
The AD9244 is a high performance, single-supply 14-bit ADC. In addition to high dynamic range Nyquist sampling, it is designed for excellent IF undersampling performance with an analog input as high as 240 MHz. The AD9244 uses a calibrated 10-stage pipeline architecture with a patented wideband, input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC along with a switched capacitor DAC and interstage residue amplifier (MDAC). The MDAC amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. While the converter captures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be fully processed and appear at the output as illustrated in Figure 1. This latency is not a concern in many applications. The digital output, together with the OTR indicator, is latched into an output buffer to drive the output pins. The output drivers of the AD9244 can be configured to interface with 5 V or 3.3 V logic families. The AD9244 has a duty clock stabilizer (DCS) that generates its own internal falling edge to create an internal 50% duty cycle clock, independent of the externally applied duty cycle. Control of straight binary or twos complement output format is accomplished with the DFS pin. The ADC samples the analog input on the rising edge of the clock. While the clock is low, the input SHA is in sample mode. When the clock transitions to a high logic level, the SHA goes into the hold mode. System disturbances just prior to or immediately after the rising edge of the clock and/or excessive clock jitter may cause the SHA to acquire the wrong input value and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
AD9244
VIN+ 0.1 F
Figure 3a. 2 V p-p Differential Input, Common-Mode Voltage = 2 V
3.0V 1.0V 33 33 20pF VIN- REFT 2V + 10 F 0.1 F VREF SENSE REFGND REFB 0.1 F 0.1 F 10 F +
AD9244
VIN+ 0.1 F
Figure 3b. 2 V p-p Single-Ended Input, Common-Mode Voltage = 2 V
2.5V 3.0V 2.0V 33 VIN+ 50 33 2V 3.0V 3.0V 2.5V 2.0V 2.0V + 10 F 0.1 F SENSE REFGND 20pF VIN- REFT 0.1 F VREF REFB 0.1 F 10 F + 0.1 F 0.1 F
AD9244
CML
The differential input span of the AD9244 is equal to the potential at the VREF pin. The VREF potential may be obtained from the internal AD9244 reference or an external source. In differential applications, the center point of the input span is the common-mode level of the input signals. In single-ended applications, the center point is the dc potential applied to one input pin while the signal is applied to the opposite input pin. Figures 3a to 3c show various system configurations.
Figure 3c. 2 V p-p Differential Input, Common-Mode Voltage = 2.5 V
Figure 4 is a simplified model of the AD9244 analog input, showing the relationship between the analog inputs, VIN+, VIN-, and the reference voltage, VREF. Note that this is only a symbolic model and that no actual negative voltages exist inside the AD9244. Similar to the voltages applied to the top and bottom of the resistor ladder in a flash ADC, the value VREF/2 defines the minimum and maximum input voltages to the ADC core.
AD9244
VIN+ +VREF/2
+ -
V
CORE
14 ADC CORE
VIN-
-VREF/2
Figure 4. Equivalent Analog Input of AD9244
REV. A
-15-
AD9244
A differential input structure allows the user to easily configure the inputs for either single-ended or differential operation. The ADC's input structure allows the dc offset of the input signal to be varied independent of the input span of the converter. Specifically, the input to the ADC core can be defined as the difference of the voltages applied at the VIN+ and VIN- input pins. Therefore, the equation VCORE = VIN + - VIN - (1) defines the output of the differential input stage and provides the input to the ADC core. The voltage, VCORE, must satisfy the condition
- VREF/ 2 < VCORE < VREF/ 2
For additional information showing the relationship between VIN+, VIN-, VREF, and the analog input range of the AD9244, see Tables I and II.
ANALOG INPUT OPERATION
Figure 5 shows the equivalent analog input of the AD9244, which consists of a 750 MHz differential SHA. The differential input structure of the SHA is flexible, allowing the device to be configured for either a differential or single-ended input. The analog inputs VIN+ and VIN- are interchangeable, with the exception that reversing the inputs to the VIN+ and VIN- pins results in a data inversion (complementing the output word).
S
(2)
where VREF is the voltage at the VREF pin. In addition to the limitations placed on the input voltages VIN+ and VIN- by Equations 1 and 2, boundaries on the inputs also exist based on the power supply voltages according to the conditions
CH S CS VIN+ CPIN, PAR VIN- CPIN, PAR S H
- +
AGND - 0.3 V < VIN + < AVDD + 0.3 V AGND - 0.3 V < VIN - < AVDD + 0.3 V
(3)
CS
CH
S
where AGND is nominally 0 V and AVDD is nominally 5 V. The range of valid inputs for VIN+ and VIN- is any combination that satisfies both Equations 2 and 3.
Figure 5. Analog Input of AD9244 SHA
Table I. Analog Input Configuration Summary
Input Connection Single-Ended
Input Range (V) Input Coupling Span (V) VIN+* VIN-* DC or AC 1.0 2.0 0.5 to 1.5 1 to 3 1.0 2.0
Input CM Voltage Comments 1.0 2.0 Best for stepped input response applications. Optimum noise performance for single-ended mode, often requires low distortion op amp with VCC > 5 V due to its headroom issues. Optimum full-scale THD and SFDR performance well beyond the ADC's Nyquist frequency. Optimum noise performance for differential mode Preferred mode for applications.
Differential
DC or AC 1.0 2.0
2.25 to 2.75 2.75 to 2.25 2.5 2.0 to 3.0 3.0 to 2.0 2.5
*VIN+ and VIN- can be interchanged if data inversion is required.
Table II. Reference Configuration Summary
Reference Operating Mode Internal Internal Internal External
Connect SENSE SENSE R1 R2 SENSE VREF
To VREF AGND VREF and SENSE
SENSE and REFGND
Resulting VREF (V) 1 2 1 VREF 2.0 VREF = (1 + R1/R2) 1 VREF 2.0
Input Span (VIN+ - VIN-) (V p-p) 1 2 1 SPAN 2 (SPAN = VREF) SPAN = EXTERNAL REF
AVDD EXTERNAL REF
-16-
REV. A
AD9244
The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 2 V input span) and matched input impedance for VIN+ and VIN-. Only a slight degradation in dc linearity performance exists between the 2 V and 1 V input spans; however, the SNR is lower in the 1 V input span. When the ADC is driven by an op amp and a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recovers, ringing may occur. To remedy the situation, a series resistor, RS, can be inserted between the op amp and the SHA input as shown in Figure 6. A shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the sampling capacitor, CS, further reducing current transients seen at the op amp's output.
VCC RS 33 RS 33 20pF VIN- VREF 10 F 0.1 F SENSE REFCOM
50 0.1 F 1k 20pF RS 33
Since not all applications have a signal precondition for differential operation, there is often a need to perform a single-ended-todifferential conversion. In systems that do not require dc coupling, an RF transformer with a center tap is the best method for generating differential input signals for the AD9244. This provides the benefit of operating the ADC in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the ADC. The differential input characterization for this data sheet was performed using the configuration in Figure 7. The circuit uses a Mini-Circuits(R) RF transformer, model T1-1T, which has an impedance ratio of 1:1. This circuit assumes that the signal source has a 50 source impedance. The secondary center tap of the transformer allows a dc common-mode voltage to be added to the differential input signal. In Figure 7, the center tap is connected to a resistor divider providing a half supply voltage. It could also be connected to the CML pin of the AD9244. It is recommended for IF sampling applications (70 MHz < fIN < 200 MHz) that the 20 pF differential capacitor between VIN+ and VIN- be reduced or removed.
AVDD 1k VIN+ REFT 0.1 F
AD9244
VIN+
VEE
+
AD9244
REFB VIN-
0.1 F
10 F
+
Figure 6. Resistors Isolating SHA Input from Op Amp
The optimum size of this resistor is dependent on several factors, including the ADC sampling rate, the selected op amp, and the particular application. In most applications, a 30 to 100 resistor is sufficient. For noise sensitive applications, the very high bandwidth of the AD9244 may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the ADC's input by forming a low-pass filter. The source impedance driving VIN+ and VIN- should be matched. Failure to provide matching may result in degradation of the SNR, THD, and SFDR performance.
Differentially Driving the Analog Inputs
0.1 F
MINI-CIRCUITS T1-1T
RS 33
Figure 7. Transformer-Coupled Input
The circuit shown in Figure 8 shows a method for applying a differential direct-coupled signal to the AD9244. An AD8138 amplifier is used to derive a differential signal from a singleended signal.
10 F + 0.1 F 0.1 F 1k 1k 5V
10 F + 0.1 F 0.1 F
The AD9244 has a very flexible input structure, allowing it to interface with single-ended or differential inputs. The optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular application's performance requirements as well as power supply options. Differential operation requires that VIN+ and VIN- be simultaneously driven with two equal signals that are 180 out of phase with each other. Differential modes of operation (ac-coupled or dc-coupled input) provide the best SFDR performance over a wide frequency range. They should be considered for the most demanding spectral-based applications (i.e., direct IF conversion to digital).
0V
1V p-p 475 50 499
499
33
AVDD VIN+ REFT
AD8138
20pF
AD9244
REFB
0.1 F + 10 F 0.1 F
VIN- 499 33
Figure 8. Direct-Coupled Drive Circuit with AD8138 Differential Op Amp
REV. A
-17-
AD9244
REFERENCE OPERATION Pin Programmable Reference
The AD9244 contains a band gap reference that provides a pinstrappable option to generate either a 1 V or 2 V output. With the addition of two external resistors, the user can generate reference voltages between 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance as described later in this section. Figure 9a shows a simplified model of the internal voltage reference of the AD9244. A reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. As stated earlier, the voltage on the VREF pin determines the full-scale differential input span of the ADC.
AD9244
TO ADC REFT 2.5V A2 REFB
By shorting the VREF pin directly to the SENSE pin, the internal reference amplifier is placed in a unity gain mode and the resulting VREF output is 1 V. By shorting the SENSE pin directly to the REFGND pin, the internal reference amplifier is configured for a gain of 2.0 and the resulting VREF output is 2.0 V.
Resistor Programmable Reference
Figure 10 shows an example of how to generate a reference voltage other than 1.0 V or 2.0 V with the addition of two external resistors. Use the equation VREF = 1 V x (1 + R1/R 2) to determine the appropriate values for R1 and R2. These resistors should be in the 2 k to 10 k range. For the example shown, R1 equals 2.5 k and R2 equals 5 k. From the equation above, the resulting reference voltage on the VREF pin is 1.5 V. This sets the differential input span to 1.5 V p-p. The midscale voltage can also be set to VREF by connecting VIN- to VREF.
3.25V 1.75V 33 20pF 2.5V 33 1.5V 10 F 0.1 F R1 2.5k R2 5k VIN- REFT VREF 0.1 F SENSE REFGND REFB 0.1 F 10 F
AD9244
VIN+ 0.1 F
VREF 1V A1 R SENSE DISABLE A1 LOGIC R REFGND
Figure 9a. Equivalent Reference Circuit
Figure 10. Resistor Programmable Reference (1.5 V p-p Input Span, Differential Input with VCM = 2.5 V)
Using an External Reference
The voltage appearing at the VREF pin and the state of the internal reference amplifier, A1, are determined by the voltage present at the SENSE pin. The logic circuitry contains comparators that monitor the voltage at the SENSE pin. The various reference modes are summarized in Table II and are described in the next few sections. The actual reference voltages used by the internal circuitry of the AD9244 appear on the REFT and REFB pins. The voltages on these pins are symmetrical about midsupply or CML. For proper operation, it is necessary to add a capacitor network to decouple these pins. Figure 9b shows the recommended decoupling network. The turn-on time of the reference voltage appearing between REFT and REFB is approximately 10 ms and should be taken into consideration in any power-down mode of operation. The VREF pin should be bypassed to the REFGND pin with a 10 F tantalum capacitor in parallel with a low inductance 0.1 F ceramic capacitor.
0.1 F VREF + 10 F 0.1 F REFT 0.1 F* + 10 F
To use an external reference, the internal reference must be disabled by connecting the SENSE pin to AVDD. The AD9244 contains an internal reference buffer, A2 (see Figure 9a), that simplifies the drive requirements of an external reference. The external reference must be able to drive a 5 k ( 20%) load. The bandwidth of the reference is deliberately left small to minimize the reference noise contribution. As a result, it is not possible to drive VREF externally with high frequencies. Figure 11 shows an example of an external reference driving both VIN- and VREF. In this case, both the common-mode voltage and input span are directly dependent on the value of VREF. Both the input span and the center of the input span are equal to the external VREF. Thus the valid input range extends from (VREF + VREF/2) to (VREF - VREF/2). For example, if the precision reference part, REF191, a 2.048 V external reference, is used, the input span is 2.048 V. In this case, 1 LSB of the AD9244 corresponds to 0.125 mV. It is essential that a minimum of a 10 F capacitor, in parallel with a 0.1 F low inductance ceramic capacitor, decouple the reference output to AGND.
VREF + VREF/2 33 20pF 33 0.1 F AVDD SENSE VIN- 0.1 F VREF REFB 0.1 F 10 F
AD9244
REFGND REFB
AD9244
VIN+ REFT + 0.1 F
0.1 F *LOCATE AS CLOSE AS POSSIBLE TO REFT/REFB PINS
VREF - VREF/2 5V 0.1 F VREF 10 F
Figure 9b. Reference Decoupling
Figure 11. Using an External Reference
-18-
REV. A
AD9244
Table III. Output Data Format
Input (V) VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN-
Condition (V)
< -VREF - 0.5 LSB
Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111
Twos Complement Mode 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111
OTR 1 0 0 0 1
= -VREF =0 = +VREF - 1.0 LSB > +VREF - 0.5 LSB
DIGITAL INPUTS AND OUTPUTS Digital Outputs
Table III details the relationship among the ADC input, OTR, and digital output format.
Data Format Select (DFS)
OTR DATA OUTPUTS 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110
+FS - 1 LSB OTR
-FS + 1/2 LSB 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 -FS -FS - 1/2 LSB +FS +FS - 1/2 LSB
The AD9244 may be programmed for straight binary or twos complement data on the digital outputs. Connect the DFS pin to AGND for straight binary and to AVDD for twos complement.
Digital Output Driver Considerations
The AD9244 output drivers can be configured to interface with 5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V, respectively. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.
Out-of-Range (OTR)
Figure 12. OTR Relation to Input Voltage and Output Data
Table IV. Output Data Format
OTR 0 0 1 1
MSB 0 1 0 1
Analog Input Is Within Range Within Range Underrange Overrange
An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OTR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OTR has the same pipeline latency as the digital data. OTR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in Figure 12. OTR will remain high until the analog input returns to within the input range and another conversion is completed. By logically AND-ing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table IV is a truth table for the overrange/underrange range circuit in Figure 13, which uses NAND gates. Systems requiring programmable gain conditioning of the AD9244 can, after eight clock cycles, detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration.
MSB OTR MSB
OVER = 1
UNDER = 1
Figure 13. Overrange/Underrange Logic
Digital Output Enable Function (OEB)
The AD9244 has three-state ability. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. It is not intended for rapid access to the data bus. Note that OEB is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage.
REV. A
-19-
AD9244
CLOCK OVERVIEW Clock Input Considerations
The AD9244 has a flexible clock interface that accepts either a single-ended or differential clock. An internal bias voltage facilitates ac coupling using two external capacitors. To remain backward compatible with the single-pin clock scheme of the AD9226, the AD9244 can be operated with a dc-coupled, single-pin clock by grounding the CLK- pin and driving CLK+. When the CLK- pin is not grounded, the CLK+ and CLK- pins function as a differential clock receiver. When CLK+ is greater than CLK-, the SHA is in hold mode; when CLK+ is less than CLK-, the SHA is in track mode (see timing in Figure 14). The rising edge of the clock (CLK+ - CLK-) switches the SHA from track to hold and timing jitter on this transition should be minimized, especially for high frequency analog inputs. It is often difficult to maintain a 50% duty cycle to the ADC, especially when driving the clock with a single-ended or sine wave input. To ease the constraint of providing an accurate 50% clock, the ADC has an optional internal duty cycle stabilizer (DCS) that allows the rising clock edge to pass through with minimal jitter and interpolates the falling edge, independent of the input clock falling edge. The DCS is described in greater detail in a later section.
Clock Input Modes
The analog input is sampled on the rising edge of the clock. Timing variations, or jitter, on this edge causes the sampled input voltage to be in error by an amount proportional to the slew rate of the input signal and to the amount of the timing variation. Thus, to maintain the excellent high frequency SFDR and SNR characteristics of the AD9244, it is essential that the clock edge be kept as clean as possible. The clock should be treated like an analog signal. Clock drivers should not share supplies with digital logic or noisy circuits. The clock traces should not run parallel to noisy traces. Using a pair of symmetrically routed, differential clock signals can help to provide immunity from common-mode noise coupled from the environment. The clock receiver functions like a differential comparator. At the CLK inputs, a slowly changing clock signal will result in more jitter than a rapidly changing one. Driving the clock with a low amplitude sine wave input is not recommended. Running a high speed clock through a divider circuit will provide a fast rise/fall time, resulting in the lowest jitter in most systems.
Figures 15a to 15e illustrate the modes of operation of the clock receiver. Figure 15a shows a differential clock directly coupled to CLK+ and CLK-. In this mode, the common mode of the CLK+ and CLK- signals should be close to 1.6 V. Figure 15b illustrates a single-ended clock input. The capacitor decouples the internal bias voltage on the CLK- pin (about 1.6 V), establishing a threshold for the CLK+ pin. Figure 15c provides backward compatibility with the AD9226. In this mode, CLK- is grounded and the threshold for CLK+ is 1.5 V. Figure 15d shows a differential clock ac-coupled by connecting through two capacitors. AC coupling a single-ended clock can also be accomplished using the circuit in Figure 15e. When using the differential clock circuits of Figure 15a or Figure 15d, if CLK- drops below 250 mV, the mode of the clock receiver may change, causing conversion errors. It is essential that CLK- remain above 250 mV when the clock is ac-coupled or dc-coupled.
CLK+
AD9244
CLK-
Figure 15a. Differential Clock Input--DC-Coupled
CLK+
AD9244
1.6V 0.1 F AGND CLK-
CLK-
Figure 15b. Single-Ended Clock Input--DC-Coupled
CLK+ SHA IN HOLD SHA IN TRACK
CLK+
AD9244
CLK- CLK+
CLK-
AGND
Figure 14. SHA Timing Figure 15c. Single-Ended Input--Retains Pin Compatibility with AD9226
-20-
REV. A
AD9244
speed. When the stabilizer is disabled, the internal switching will be directly affected by the clock state. If CLK+ is high, the SHA will be in hold mode; if CLK+ is low, the SHA will be in track mode. TPC 16 shows the benefits of using the clock stabilizer. Connecting the DCS pin to AVDD implements the internal clock stabilization function in the AD9244. If the DCS pin is connected to ground, the AD9244 will use both edges of the external clock in its internal timing circuitry (see Specifications for timing requirements).
GROUNDING AND DECOUPLING Analog and Digital Grounding
CLK+
AD9244
CLK- 100pF - 0.1 F
Figure 15d. Differential Clock Input--AC-Coupled
0.1 F
CLK+
AD9244
1.6 V 0.1 F AGND CLK-
Proper grounding is essential in high speed, high resolution systems. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power distribution. The use of power and ground planes offers distinct advantages, including: * * * The minimization of the loop area encompassed by a signal and its return path. The minimization of the impedance associated with ground and power paths. The inherent distributed capacitor formed by the power plane, PCB material, and ground plane.
Figure 15e. Single-Ended Clock Input--AC-Coupled
Clock Power Dissipation
Most of the power dissipated by the AD9244 is from the analog power supplies. However, lower clock speeds will reduce digital supply current. Figure 16 shows the relationship between power and clock rate.
600 550 500
POWER - mW
AD9244-65
It is important to design a layout that minimizes noise from coupling onto the input signal. Digital input signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9244 features separate analog and digital ground pins, it should be treated as an analog component. The AGND and DGND pins must be joined together directly under the AD9244. A solid ground plane under the ADC is acceptable if the power and ground return currents are carefully managed.
Analog Supply Decoupling
450 400 350 300 250 200 AD9244-40
0
10
20
30 40 50 SAMPLE RATE - MHz
60
70
The AD9244 features separate analog and digital supply and ground circuits, helping to minimize digital corruption of sensitive analog signals. In general, AVDD (analog power) should be decoupled to AGND (analog ground). The AVDD and AGND pins are adjacent to one another. Figure 17 shows the recommended decoupling for each pair of analog supplies; 0.1 F ceramic chip and 10 F tantalum capacitors should provide adequately low impedance over a wide frequency range. The decoupling capacitors (especially 0.1 F) should be located as close to the pins as possible.
10 F + AVDD 0.1 F*
Figure 16. Power Consumption vs. Sample Rate
Clock Stabilizer (DCS)
AD9244
AGND
The clock stabilizer circuit in the AD9244 desensitizes the ADC from clock duty cycle variations. System clock constraints are eased by internally restoring the clock duty cycle to 50%, independent of the clock input duty cycle. Low jitter on the rising edge (sampling edge) of the clock is preserved while the falling edge is generated on-chip. It may be desirable to disable the clock stabilizer and may be necessary when the clock frequency is varied or completely stopped. Note that stopping the clock is not recommended with ac-coupled clocks. Once the clock frequency is changed, over 100 clock cycles may be required for the clock stabilizer to settle to the new
*LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS
Figure 17. Analog Supply Decoupling
Digital Supply Decoupling
The digital activity on the AD9244 falls into two categories: correction logic and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses when the output bits change state. The size and duration of these currents are a function of the load on the output bits; large capacitive loads should be avoided.
REV. A
-21-
AD9244
For the digital decoupling shown in Figure 18, 0.1 F ceramic chip and 10 F tantalum capacitors are appropriate. The decoupling capacitors (especially 0.1 F) should be located as close to the pins as possible. Reasonable capacitive loads on the data pins are less than 20 pF per bit. Applications involving greater digital loads should consider increasing the digital decoupling and/or using external buffers/latches. A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the power supply connector to reduce low frequency ripple to insignificant levels.
10 F + DRVDD 0.1 F*
AD9244
DGND
*LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS
Figure 18. Digital Supply Decoupling
CML
from single-ended signals to differential. Optimal AD9244 performance is achieved above 500 kHz by using the input transformer. To drive the AD9244 via the transformer, connect solderable Jumpers JP45 and JP46. DC bias is provided by the Resistors R8 and R28. The evaluation board has positions for through-hole and surfacemount transformers. For applications requiring lower frequencies or dc applications, the AD8138 can be used. The AD8138 will provide good distortion and noise performance, as well as input buffering, up to 30 MHz. For more information, refer to the AD8138 data sheet. To use the AD8138 to drive the AD9244, remove the transformer (T1 or T4) and connect solderable Jumpers JP42 and JP43. The AD9244 can be driven single-ended directly via S3 and can be ac-coupled or dc-coupled by removing or inserting JP5. To run the evaluation board in this way, remove the transformer (T1 or T4) and connect solderable Jumpers JP40 and JP41. The Resistors R40, R41, R8, and R28 are used to bias the AD9244 inputs to the correct common-mode levels in this application.
Reference Configuration
The AD9244 has a midsupply reference point. This is used within the internal architecture of the AD9244 and must be decoupled with a 0.1 F capacitor. It will source or sink a load of up to 300 A. If more current is required, the CML pin should be buffered with an amplifier.
VR
As described in the Analog Input and Reference Overview section earlier in this data sheet, the AD9244 can be configured to use its own internal or an external reference. An external reference, D3, and reference buffer, U5, are included on the AD9244 evaluation board. Jumpers JP8 and JP22-JP24 can be used to select the desired reference configuration (Table VI).
Clock Configuration
VR is an internal bias point on the AD9244. It must be decoupled to AGND with a 0.1 F capacitor.
CML 0.1 F VR 0.1 F
AD9244
Figure 19. CML/VR Decoupling
EVALUATION BOARD Analog Input Configuration
Table V provides a summary of the analog input configuration. The analog inputs of the AD9244 on the evaluation board can be driven differentially through a transformer via Connector S4, or the AD8138 amplifier via Connector S2, or driven single-ended directly via Connector S3. When using the transformer or AD8138 amplifier, a single-ended source may be used as both of these devices are configured on the AD9244 evaluation board to convert
The AD9244 evaluation board was designed to achieve optimal performance as well as to be easily configurable by the user. To configure the clock input, begin by connecting the correct combination of solderable Jumpers JP11-JP15 (Table VII). The specific jumper configuration is dependent on the application and can be determined by referring to the clock input modes section. If the differential clock input mode is selected, an external sine wave generator applied to S5 can be used as the clock source. The clock buffer/drive MC10EL16 from ON Semiconductor is used on the evaluation board to buffer and square the clock input. If the single-ended clock configuration is used, an external clock source can be applied to S1. The AD9244 evaluation board generates a buffered clock at TTL/CMOS levels for use with a data capture system, such as the HSC-ADC-EVAL-SC system. The clock buffering is provided by U4 and U7 and is configured by Jumpers JP3, JP4, JP9, and JP18 (Table VII).
-22-
REV. A
AD9244
Table V. Analog Input Jumper Configuration
Input Connector Differential: Transformer Differential: Amplifier Single-Ended S4 S2 S3
Jumpers 45, 46 42, 43 5, 40, 41
Notes R8, R28 Provide DC Bias. Optimal for 500 kHz+. Remove T1 or T4. Used for low input frequencies. Remove T1 or T4. JP5: connected for dc-coupled, not connected for ac-coupling.
Table VI. Reference Jumper Configuration
Reference Internal Internal Internal External
Voltage 2V 1V 1 V VREF 2 V 1 V VREF 2 V
Jumpers 23 24 25 8, 22
Notes JP8 Not Connected. JP8 Not Connected. JP8 Not Connected. VREF = 1 + R1/R2. Set VREF with R26.
Table VII. Clock Jumper Configuration
Input Connector DUT Clock Differential Single-Ended Data Capture Clock Internal Diff DUT Clock SE DUT Clock External S5 S1
Jumpers 11, 13 12, 15
NA NA S6
9, 18A 9, 18B 3 or 4
5V + - -
5V + -
3V + -
3V +
AVDD REFIN SIGNAL SYNTHESIZER 2.5MHz, 0.8V p-p HP8644 CLK SYNTHESIZER 65MHz, 1V p-p HP8644 2.5MHz BAND-PASS FILTER S4 INPUT xFMR S1/S5 INPUT CLOCK
GND DUT GND DUT AVDD DVDD
DVDD
AD9244
EVALUATION BOARD
10MHz REFOUT
CLOCK DIVIDER
OUTPUT BUSS J1
DSP EQUIPMENT
Figure 20. Evaluation Board Connections
REV. A
-23-
AD9244
5 AVDD OUT 2 -IN DUTAVDD JP23 JP22 TP5 WHT U5 AD822 1 3 +IN JP8
+IN
AGND; 4 AVDD; 8 AGND; 4 AVDD; 8
OUT
7
6
-IN
U5 AD822 R20 2k
R16 2.55k
U1
CW
AVDD R26 2k C29 0.1 F JP24 R4 DNP C35 0.1 F FBEAD RED DUTAVDD C59 0.1 F JP12 SECLK JP11 FBEAD RED AVDD SHEET2 JP14 DUTAVDD C38 0.1 F C42 0.001 F C41 0.001 F JP13 FBEAD RED JP15 C30 0.1 F DUTDRVDD FBEAD RED DVDD C14 0.1 F TP11 TP12 TP13 TP14 BLK BLK BLK BLK L4 TP4 C1 10 F 10V C37 0.1 F C45 0.001 F DUTDRVDD C53 0.1 F L3 TP3 DIFFB C23 10 F 10V C52 0.1 F L2 TP1 DIFFA C32 0.1 F C50 0.1 F VIN+ SHEET3 VIN- C33 0.1 F C34 0.1 F C20 0.1 F 10V L1 TP2 C21 10 F 10V R17 2k R3 DNP JP25
1
C22 10 F 10V C36 0.1 F C39 0.001 F
AD9226/AD9244
C27 10 F 10V
C28 0.1 F
2
D3
C56 + 10 F 10V
C57 0.1 F
DUTAVDDIN TB1 2
AVDD JP6 JP1 JP2
C58 22 F 25V
AGND TB1 3
Figure 21. AD9244 Evaluation Board, ADC, External Reference, and Power Supply Circuitry
-24-
OTRO D13O D12O D11O D10O D9O D8O D7O D6O D5O D4O D3O D2O D1O D0O
AVDDIN TB1 1
C47 22 F 25V
AVDD OTR AVDD MSB-D13 AGND D12 AGND D11 SENSE D10 VREF D9 REFGND D8 REFB D7 REFB D6 REFT D5 REFT D4 CML D3 VIN+ D2 VIN- D1 CLK+ LSB-D0 CLK- NIC AGND OEB AGND VR AVDD DFS AVDD DCS DGND AGND
R42 1k R6 1k
DRVDD DRVDD DGND
DRVDDIN TB1 5
3 4 1 2 36 37 38 39 40 41 42 45 46 47 7 6 32 33 31 34 30 29 23 22 28 27 26 25 24 21 20 19 18 17 16 13 12 11 10 8 9 48 35 43 5 44 NIC 15 DRVDD 14 DGND
C2 0.1 F
C48 22 F 25V
R10 1k
AGND TB1 4
C40 0.001 F
DVDDIN TB1 6
C6 22 F 25V
REV. A
REV. A
DVDD C61 0.1 F R39 49.9 OTRO D13O D12O D11O
19 10 1 RP1 22 2 RP1 22 3 RP1 22 4 RP1 22 15 14 5 RP1 22 16 15 14 13 12 1 2 RP4 1 22 8 RP3 4 22 5 1 RP3 3 22 6 RP3 2 22 7 RP3 1 22 8
DIFFCLK S5 OTR D13 D12 D11 D13 D10 D12 D11 D10 D9 A5 A6 A7 A8 D7 D8 D7 D6 D5 D4 C5 C11 0.1 F 10 F 10V + U7 74VHC541
1 8 9 7 6 5 4 3 2
R11 49.9 R45 10k AVDD G1 G2 A1 A2 Y2 Y3 Y4 Y5 Y6 Y7 Y8
16 17
R43 100 U6 74VHC541 VCC GND 18 Y1
20
R44 CW 100
C4 C12 0.1 F 10 F 10V + 2 4 6 MSB 8 10 12 14 16
13 12 11 6 RP1 22 7 RP1 22 8 RP1 22 11 10 9
1 3 5 7 9 11 13 15 18 20 22 24 26 28 30 32 17 19 21 23 25 27 29 31
AVDD C46 0.1 F R23 33
8 7
U3 MC10EL16 D10O R38 10k D8O R30 10k C60 0.01 F D7O
RP5 1 22 8 RP4 4 22 5 RP4 3 22 6
DIFFA
6 3 4 5 RP4 2 22 7
DIFFB C49 0.1 F A4 AVDD R12 113 R13 113 R15 90 D5O AVDD C18 0.1 F R19 4k AVDD D3O D2O R7 22 SECLK D0O JP4 3 C31 0.1 F 74VHC04
1 CW RP5 2 22 7 RP5 3 22 6 RP5 4 22 5
R25 33 D9O D8 D9 Y3
VCC Q Q VEE
RESET CLK CLK VBB
AVDD C17 0.1 F C19 0.1 F D6O D6
R14 90
HEADER RIGHT ANGLE MALE NO EJECTORS
Figure 22. AD9244 Evaluation Board, Clock Input, and Digital Output Buffer Circuitry
D4O C26 10 F 10V
RP6 1 22 8 RP6 2 22 7 RP6 3 22 6
-25-
R2 5k U3 DECOUPLING R18 4k D3 D2 D1
RP6 4 22 5
G1
19
VCC D5 D4 D3 D0 D2 D1 D0 OTR
2 3 4
20 10
34 36 G2 A1 A2 Y3
5 6 7 8 9
33 35 GND 18 Y1 Y2 Y3 A4 A5 A6 A7 A8 Y4 Y5 Y6 Y7 Y8
17 16 1 RP2 22 2 RP2 22 3 RP2 22 16 15 14
SECLK S1 WHT TP7 1 74VHC04 R9 22 JP9 74VHC04 R1 49.9 U4 4 JP3 C13 0.1 F U4 2 D1O AVDD; 14 AGND; 7 U4 5 6
38 40
15 14 13 12 11 4 RP2 22 5 RP2 22 6 RP2 22 7 RP2 22 8 RP2 22 13 12 11 10 9
37 39 SAM040RAM J1
OTR CLK U4 AVDD C10 0.1 F C3 10 F 10V 9
74VHC04 U4 13 12
CW
8 74VHC04 U4 11 10
3
B
2 A
S6 DATACLK R27 2k
JP18 R29 49.9
AVDD
U4 DECOUPLING
74VHC04
AD9244
AD9244
JP5 SINGLE INPUT S3 R5 49.9 C15 10 F 10V C9 0.33 F R41 1k JP42 JP40 AVDD R32 10k JP45 C69 0.1 F R37 499 4 OUT+ VOCM OUT- 5 2 R46 33 R33 10k C8 0.1 F JP41 JP43 JP45 R21 33 R22 33 C43 DNP C44 DNP VIN+ C24 20pF SHEET 1 VIN- R40 1k AVDD C7 0.1 F
AVDD
3 1 V+ -IN
AMP INPUT
S2 R31 49.9
R34 523 8 R35 499
U2 AD8138
+IN V- 6
R47 33 ADT4-6T
R36 499
1
P
T4
S
6 5
AVDD
3
4
NC= 2 XFMRINPUT S4 R24 49.9
5 P CW
T1-1TX65
S
1 2 3
R28 2k
NC = 5
4
T1
R8 500
C25 0.33 F
C16 0.1 F
Figure 23. AD9244 Evaluation Board, Analog Input Circuitry
-26-
REV. A
AD9244
Figure 24. AD9244 Evaluation Board, PCB Assembly, Top
REV. A
-27-
AD9244
Figure 25. AD9244 Evaluation Board, PCB Assembly, Bottom
-28-
REV. A
AD9244
Figure 26. AD9244 Evaluation Board, PCB Layer 1 (Top)
REV. A
-29-
AD9244
Figure 27. AD9244 Evaluation Board, PCB Layer 2 (Ground Plane)
-30-
REV. A
AD9244
Figure 28. AD9244 Evaluation Board, PCB Layer 3 (Power Plane)
REV. A
-31-
AD9244
Figure 29. AD9244 Evaluation Board, PCB Layer 4 (Bottom)
-32-
REV. A
AD9244
OUTLINE DIMENSIONS 8-Lead Low Profile Quad Flat Package [LQFP] (ST-48)
Dimensions shown in millimeters
0.75 0.60 0.45 1.60 MAX
48 1
9.00 BSC SQ
37 36
1.45 1.40 1.35
10 6 2
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
PIN 1
TOP VIEW
(PINS DOWN)
7.00 BSC SQ
VIEW A
12 13 24 25
0.15 0.05
SEATING PLANE
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. A
-33-
AD9244 Revision History
Location 6/03--Data Sheet changed from REV. 0 to REV. A Page
Changes to AC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
-34-
REV. A
-35-
-36-
C02404-0-6/03(A)

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